spsemi ... www.spsemi.cn page 1 of 3 electro-static discharge for aotomobile AUSD12FB low capacitance tvs diode features 350 watts peak pulse power per line (tp=8/20s) protects one i/o or power line bidirectional) ( low clamping voltage working voltages: 12v low leakage current esd/AUSD12FB iec compatibility iec61000-4-2 (esd) 30kv (air), 30kv (contact) iec61000-4-4 (eft) 40a (5/50s) mechanical characteristics jedec sod-323 package molding compound flammability rating:ul 94v-o weight 5 millgrams(approximate) quantity per reel:3000pcs reel size:7 inch lead finish:lead free applications cell phone handsets and accessories microprocessor based equipment personal digital assistants(pda's) notebooks,desktops,and servers portable instrumentation peripherals usb interface sod-323 pin configuration 1 2 12 rev 2017 07 24 aec-q101
spsemi www.spsemi.cn page 2 of 3 parameter symbol value units peak pulse power(tp=8/20s) lead soldering temperature operating temperature range storage temperature range p pp t l t j t stg 350 260(10 sec.) -55~150 -55~150 watts maximum ratings (t =25 unless otherwise noted ) a electrical characteristics (t =25 unless otherwise specified ) a esd/AUSD12FB ratings and characteristic curves fig.1 pulse waveform 5 010 30 15 0 10 time( ) s 20 25 20 30 40 50 60 70 80 90 100 110 percent of i pp t=i /2 d pp waveform parameters: tr=8s t =20s d e -1 ... parameter symbol conditions units min. max. AUSD12FB(marking:dc) reverse stand-off voltage breakdown voltage reverse leakage current junction capacitance clamping voltage i r c i/o v rwm v br v c 12 19 30 1 1.5 i=1ma t i =1a,tp=8/20s pp i =7a,tp=8/20s pp @v rwm 13.3 v v v v a f p 0vdc,f=1mhz between i/o pins and gnd rev 2017 07 24 fig.2 non-repetitive pulse power vs.pulse time 0 1 0.01 pulse duration-tp( ) s 10 0.1 1 peak pulse power-p (kw) pp 100 1000 10
spsemi www.spsemi.cn page 3 of 3 esd/AUSD12FB dimensions(sod-323) sod-323 recommended mounting pad layout 2.85 0.112 0.83 0.033 0.63 0.025 dimensions in ( ) millimeters inches d h e e b 1 2 a1 c l a a3 dim a a1 a3 b c d e l h e millimeters min 0.80 0.00 0.25 0.089 1.60 1.15 0.08 2.30 max 1.00 0.10 0.40 0.177 1.80 1.35 2.70 min 0.031 0.000 0.010 0.003 0.062 0.045 0.003 0.090 max 0.040 0.004 0.016 0.007 0.070 0.053 0.105 inches 0.15ref 0.006ref 1.60 0.063 application information pcb layout recommendations the location and circuit board layout is critical to maximize the effectiveness of the lin protection circuit. the following guidelines are recommended: locate the protection devices as close as possible to the lin connector. this allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the pcb. minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. avoid running protection conductors in parallel with unprotected conductors use ground planes wherever possible to reduce the parasitic capacitance and inductance of the pcb that degrades the effectiveness of a filter device. using shared transient return paths to a common ground point. lin protection ... ic AUSD12FB lin bus rev 2017 07 24
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